1. Field of the Invention
This invention presents a novel technique for the in-situ monitoring of lateral encroachment during etch processes, and particularly to a method and system implementing an in-line CD SEM or any other metrology tool capable of making line roughness measurement to measure and control the etch process by making a line width roughness measurement (LWR) in a lateral implant/dual spacer encroachment region of interest. The magnitude of the line width roughness enables early detection of a process excursion.
2. Description of the Prior Art
In semiconductor manufacturing, lateral implant/dual spacer encroachment in a dual spacer process is severely detrimental to device functionality, specifically device threshold voltage (Vth). Currently, there is no way of monitoring this in an automated and reliable fashion other than at the time of electrical test which may take months later to perform. Detecting encroachment much sooner than at electrical test is very desirable. An in-line measurement after the structure of interest is created with fast feedback and turnaround time is needed in order to determine device functionality.
FIG. 1 illustrates cross-section view of both a pFET device 10 and an nFET device 20 formed in respective pFET device and nFET device regions 12, 22 on a semiconductor substrate. As shown in FIG. 1, a dual spacer structure 50, formed according to known techniques such as described in detail in commonly-owned, co-pending U.S. patent application Ser. No. 10/277,907 (U.S. Patent Application Publication No. U.S. 2004/0075151 A1), the whole contents and disclosure of which is incorporated by reference as if fully set forth herein, extends from the pFET device 10 in the pFET region 12 through a transition region 75 to the nFET device 20 in the nFET region 22. As described in co-pending U.S. patent application Ser. No. 10/277,907, the dual spacer comprises two different spacer thicknesses for nFET and pFET devices and FIG. 1 depicts the desirable condition of a structure exhibiting no encroachment in either nFET and pFET devices. In the transition region 75, the thickness of the dual spacer 50 gradually thins as the spacer transitions from the pFET to the nFET device. A particular series of processing steps involved in the fabrication of the dual spacer is now described: In these series of steps, after deposition of a spacer nitride, for example, by PECVD, and deposition of a further dual spacer ozone TEOS and TEOS spacer etch, a Dual Spacer (DS) mask is patterned and developed over the pFET device and an etch process is performed, e.g., implementing a wet etch, however, as would be known to skilled artisans, other types of etch processes (e.g., dry-etch) are contemplated. The etch is performed to remove the TEOS spacer (e.g., oxide) from the nFET. During the wet etch, liquid encroaches under a resist layer that etches the TEOS spacer oxide towards the pFET thus, resulting in spacer thinning in a transition region. If the transition region encroaches onto the pFET device region, the variation in spacer thickness causes pFET (threshold voltage) Vt spreading. For example, spacer thickness variation through oxide spacer RIE-introduced center/edge variation resulting in pFET Vt variation from about 80 mV from an even spacer to 200 mV for thickness variation in spacer. An encroachment causing spacer thinning would also translate to pFET Vt variations. Additionally, the performance of the device may be degraded.
To illustrate the problem, FIG. 2(a) depicts an example dual spacer structure exhibiting encroachment into the pFET device region 12, and FIG. 2(b) depicts an example dual spacer structure exhibiting encroachment into the nFET device region 22. As shown in FIGS. 2(a) and 2(b), encroachment into the pFET region shows the transition region of the dual spacer shifted 50′ while encroachment into the nFET region shows the transition region of the dual spacer shifted 50″. Both of these encroachments result in reduced device performance, however, typically it is never known until electrical device testing is performed, some one hundred or more processing steps later.
It would be highly desirable to provide a process that employs an in-line CD SEM to measure and control the dual spacer process by making a line width roughness measurement (LWR) in the region of interest, i.e., transition region. This measurement is made after the dual spacer is created, well before electrical test, thus enabling detection of an early process excursion.